Ultrashort channel lengths are needed for high performance mm-wave transistors required for 5G communication technologies. Typically, the channel lengths needed for such applications are approximately 40 nm or less. Forming such small channel lengths requires expensive masks and lithographic solutions.
Additionally, transistors used in such applications are also expected to handle voltages that are typically larger than what is used for advanced silicon nodes. Due to its wide bandgap and high critical breakdown electric field, gallium nitride (GaN) transistors are great candidates for high voltage applications. However, simple transistor architecture, namely, having a single gate, source and drain, is not able to take advantage of these electrical properties. Such GaN transistors fall short of realizing the maximum breakdown voltage dictated by the material properties of GaN because drain electric field lines concentrate at the edge of the gate and cause premature breakdown. The concentration of electric field lines is the result of complex interactions in the device and is typically experienced by most transistors regardless of material used for the channel. However, the electric field line concentration is particularly problematic in GaN transistors due to the high voltages. Accordingly, high voltage transistors may accommodate the electric field line concentration by forming field plates on the gate-to-drain region. The formation of these field plates requires additional patterning operations.